1. Field of the Invention
The present invention generally relates to a temperature compensated self-refresh circuit, and more specifically, to a technology of changing a self-refresh cycle depending on temperature in a low power semiconductor memory product to generate a stable refresh cycle corresponding to a process skew and an external power.
2. Background of the Related Art
In general, a self-refresh operation means that a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) performs a refresh operation automatically with a predetermined cycle (basic cycle) at a standby mode in order to maintain data stored in a memory cell.
Since a refresh cycle is determined in case that temperature is high in a self-refresh mode, it is not necessary to consider that a refresh cycle becomes longer when temperature is low. However, unnecessary current is consumed because the refresh cycle is generated as it is when temperature is high.
FIG. 1 is a circuit diagram illustrating a conventional temperature compensated self-refresh circuit that senses temperature change in a chip to regulate a self-refresh cycle automatically.
The conventional temperature compensated self-refresh circuit comprises a comparison unit 1, a reference voltage generating unit 2, a logic unit 3 and a temperature sense unit 4.
Here, the comparison unit 1 comprises PMOS transistors P1, P2, NMOS transistors N1˜N3, and capacitors C1, C2. A common gate of the PMOS transistors P1 and P2 is connected to a drain of the PMOS transistor P2, and a power voltage V is applied through a common source.
The NMOS transistor N1, which is connected between the PMOS transistor P1 and the NMOS transistor N3, has a gate connected a node (A). The NMOS transistor N2, which is connected between the PMOS transistor P2 and the NMOS transistor N3, has a gate connected to a node (B). The NMOS transistor N3, which is connected between the NMOS transistors N1, N2 and a ground voltage terminal, has a gate to receive a control signal VLR.
The capacitor C1 is connected between the node (A) and the ground voltage terminal, and the capacitor C2 is connected between the node (B) and the ground voltage terminal.
The reference voltage generating unit 2 comprises NMOS transistors N4 and N5 which are connected serially between the power voltage V terminal and the ground voltage terminal. The NMOS transistor N4, which is connected between the power voltage V terminal and the node (B), has a gate connected in common to a source. The NMOS transistor N5, which is connected between the node (B) and the ground voltage terminal, has a gate connected to the node (B).
The logic unit 3 comprises inverters IV1˜IV4, and a NAND gate ND1. The inverters IV1˜IV3 invert and delay an output signal from the comparison unit 1. The NAND gate ND1 performs a NAND operation on a temperature sense operation signal TEMPON, an oscillating strobe signal TOSCRSTB and an output signal from the inverter IV3. The inverter IV4 inverts an output signal from the NAND gate ND1.
The temperature sense unit 4 comprises PMOS transistors P3, P4, NMOS transistors N6˜N8, and an inverter IV5.
The PMOS transistor P3, which is connected between the power voltage V terminal and a source of the NMOS transistor N6, has a gate to receive an output signal from the inverter IV4. The PMOS transistor P4, which is connected between the power voltage V terminal and the node (A), has a gate to receive the output signal from the inverter IV4.
The NMOS transistors N6˜N8 are connected serially between the node (A) and the ground voltage terminal. A gate of the NMOS transistor N6 is connected to the node (A), and a drain of the NMOS transistor N7 is connected in common to a gate of the NMOS transistor N7. A gate of the NMOS transistor N8 is connected to the output signal from the inverter IV4. The inverter IV5 inverts an output signal from the inverter IV4 to output the oscillating signal TEMPOSC.
Hereinafter, the operation of the conventional temperature compensated self-refresh circuit is described with reference to FIG. 2 that shows a voltage waveform diagram.
When the temperature sense operation signal TEMPON is applied, the node (A) transits from a power voltage level (1.5V) to a floating state. As a result, current applied to the node (A) flows through the NMOS transistors N6 and N7, which are connected with a diode type, into the ground voltage terminal.
Thereafter, when the node (A) is below a voltage level (0.75V) of the node (B) which is a reference voltage of the comparison unit 1, the oscillating signal TEMPOSC is outputted with a high pulse.
Here, when temperature rises, a threshold voltage of the NMOS transistors N6 and N7 which are a double structured diode type becomes lower. As a result, while current rises, the voltage level of the node (A) reaches rapidly a reference voltage level of the comparison unit 1, so that the oscillating signal TEMPOSC is outputted with a high pulse. Thus, as temperature becomes higher, a cycle of the oscillating signal TEMPOSC becomes faster.
However, in the conventional temperature compensated self-refresh circuit, the threshold voltage and the current of the NMOS transistors N6 and N7 are both changed as a process skew is varied. As a result, when the diode of the NMOS transistors N6 and N7 is a double structure by change of the process skew, a voltage change of 2*ΔV is generated, so that the cycle of the oscillating signal TEMPOSC makes a difference of more than 7 times.
In order to reduce a process skew in the conventional temperature compensated self-refresh circuit, a circuit which employs a reference voltage VDL_S with a Widlar type in the reference voltage generating unit 2 has been disclosed. This conventional circuit supplies the predetermined reference voltage VDL_S generated internally in the node (B) to reduce a voltage change of 2*ΔV−ΔV=ΔV.
However, as shown in FIG. 3, when processes of a NMOS transistor and a PMOS transistor are SS and FF, voltage change of the Widlar type is actually reduced, but voltage change in SF and FS becomes larger.
That is, in the conventional temperature compensated self-refresh circuit, the voltage change becomes larger because the skew is changed depending on the processes of the PMOS transistor and the NMOS transistor. As a result, a self-refresh cycle of the conventional circuit is changed depending on the process skew and the voltage change.